sots-re/tools
alex a4a1d373f1 RB: replay a recorded turn's commands -- ModCount is reachable, and the rates frame's memory order is not its wire order
sots_turn --turn-commands puts /Sim/ModCount on the original's 24 with zero residual, closing
the one leaf that has been unreachable from a save all campaign. Canonical pair 108 -> 62,
closed 46, regressed 0, fresh build directory.

The .tcb capture format (line-oriented, parser-free, '?' for a field the instrument could not
read, per-client AI seeds), a converter from lane L4's shim dump, and an adapter from lane CB's
JSON capture -- CB's stays the capture of record, .tcb stays the engine's input, and the two
paths produce byte-identical replays.

A falsified prediction paid for itself: the first run regressed two leaves because list 5's
element is decoded in MEMORY order, and the memory order of the rates frame is NOT its wire
order. Memory member 1 is wire member SRsc; six members unread. Lane CB's decoder has the same
defect and should drop its list-5 record.

Two new addresses (the second and third gate-loop heads) in ghidra/addresses.d/lane-rb.json.
2026-09-08 19:01:35 -04:00
..
aiorders_to_tcb.py RB: replay a recorded turn's commands -- ModCount is reachable, and the rates frame's memory order is not its wire order 2026-09-08 19:01:35 -04:00
cache_functions.py lane X: x86 displacement xref scanner; pin sizeof(ObservedTech) and its append site 2026-09-08 04:44:18 -04:00
dashboard.py lane S2: the standalone scaffold, and the measured distance to the byte-match 2026-09-08 10:35:56 -04:00
DASHBOARD_README.md lane S2: the standalone scaffold, and the measured distance to the byte-match 2026-09-08 10:35:56 -04:00
displacement.py tools/displacement.py: the honest progress metric - what fraction of the game runs on our code, by rung, with coverage caveats attached 2026-09-08 13:08:06 -04:00
gen_addresses.py gen_addresses: detect same-address-different-name; 13 vocabulary forks resolved across 8 fragments 2026-09-08 16:54:05 -04:00
gen_stream_schema.py lane G: wire-schema channel — layouts.json -> generated stream schema for sots-engine 2026-09-08 06:29:30 -04:00
max_income_oracle.py lane Y: the standalone's generator against lane Z's calibrated oracle pairs, and the tail's turn record 2026-09-08 11:40:19 -04:00
max_income_predict.py income-term: the output -> money chain read from the instruction stream; the BnkEl oracle goes 6/25 -> 25/25 2026-09-08 13:49:48 -04:00
probe_report.py lane H: five live probes, the oracle restored, and a harness perturbation bisected to one hook 2026-09-08 13:53:36 -04:00
reva_call.py reva_call.py: HTTP fallback for Ghidra when the MCP link drops; claim VM140 for recapture lane 2026-09-08 02:12:16 -04:00
rng_ledger_report.py lane Z: the RNG ledger for one strategic turn, measured end to end 2026-09-08 09:45:06 -04:00
rng_oracle_check.py lane Y: the standalone's generator against lane Z's calibrated oracle pairs, and the tail's turn record 2026-09-08 11:40:19 -04:00
rng_site_report.py Z: per-call-site ledger -- every word of a turn attributed, nothing left over 2026-09-08 10:41:54 -04:00
rtti_map.py lane D: automated struct recovery from the IStreamable serializers 2026-09-08 05:51:37 -04:00
serializers.py lane D: automated struct recovery from the IStreamable serializers 2026-09-08 05:51:37 -04:00
serializers_ghidra.py lane D: automated struct recovery from the IStreamable serializers 2026-09-08 05:51:37 -04:00
serializers_golden.py lane D: automated struct recovery from the IStreamable serializers 2026-09-08 05:51:37 -04:00
standalone_report.py determinism qualified: oracle holds only where no AI must choose; Rung B = command-stream replay, Rung C = behavioural AI; canonical pair now turn2->turn3 2026-09-08 18:02:58 -04:00
streams.py lane G: wire-schema channel — layouts.json -> generated stream schema for sots-engine 2026-09-08 06:29:30 -04:00
strfootprint.py lane S: std::string is 0x1c binary-wide; ObservedTech element fully mapped 2026-09-08 05:09:33 -04:00
tcb_from_json.py RB: replay a recorded turn's commands -- ModCount is reachable, and the rates frame's memory order is not its wire order 2026-09-08 19:01:35 -04:00
vmshot.py tools: live screen wall + contact sheet for the five lab guests 2026-09-08 16:53:04 -04:00
vmwatch-install.sh tools: live screen wall + contact sheet for the five lab guests 2026-09-08 16:53:04 -04:00
vmwatch.py tools: live screen wall + contact sheet for the five lab guests 2026-09-08 16:53:04 -04:00
vtable_map.py lane V2: vtable inversion — resolve indirect call edges image-wide 2026-09-08 12:05:05 -04:00
x86disp.py lane X: x86 displacement xref scanner; pin sizeof(ObservedTech) and its append site 2026-09-08 04:44:18 -04:00