sots-re/verify/results
Alex 5a3f986f38 lane U: the unlock cascade, implemented and live-verified
Reads: TechTree::PrereqsMet 0x0057d8e0 (AND of ORs; zero groups TRUE, an empty
group FALSE), the prerequisite layout at TechDef+0x88/+0x98, the tail collector
0x00587cc3, and the head of OnTechResearched (RecordObservedTech unconditional;
the research-event roll gated on ResT == def && ResearchRollPending).

Live: 35 compared calls over three workloads, 0 divergences, tracecmp exit 0,
End-Turn oracle hashes unchanged. The EVENT_TECHS_UNLOCKED residual lane P
predicted and lane V measured is closed by running the cascade, not by posting
on completion.

12 new addresses in ghidra/addresses.d/lane-u.json (header 615 -> 627).
2026-09-08 06:57:37 -04:00
..
compare lane U: the unlock cascade, implemented and live-verified 2026-09-08 06:57:37 -04:00
data-catalogs verify: mars data parsers proven 100% on 1595 files; catalogs; tech-tree graph 2026-09-07 15:22:55 -04:00
fpu-cw lane F: x87 precision sensitivity measured; STATE_CHECKSUM 3.5 closed 2026-09-08 05:07:53 -04:00
saves lane V: live verification of the event-posting model against an advance prediction 2026-09-08 05:59:22 -04:00
shim lane U: the unlock cascade, implemented and live-verified 2026-09-08 06:57:37 -04:00
state-checksum state-checksum: whole-state diagnostic checksum harness (lane C) 2026-09-08 03:46:34 -04:00
.keep.md scaffold RE campaign: board, backlog, findings template, verify tree 2026-09-07 14:40:44 -04:00