sots-re/verify
Alex 5a3f986f38 lane U: the unlock cascade, implemented and live-verified
Reads: TechTree::PrereqsMet 0x0057d8e0 (AND of ORs; zero groups TRUE, an empty
group FALSE), the prerequisite layout at TechDef+0x88/+0x98, the tail collector
0x00587cc3, and the head of OnTechResearched (RecordObservedTech unconditional;
the research-event roll gated on ResT == def && ResearchRollPending).

Live: 35 compared calls over three workloads, 0 divergences, tracecmp exit 0,
End-Turn oracle hashes unchanged. The EVENT_TECHS_UNLOCKED residual lane P
predicted and lane V measured is closed by running the cascade, not by posting
on completion.

12 new addresses in ghidra/addresses.d/lane-u.json (header 615 -> 627).
2026-09-08 06:57:37 -04:00
..
design-rules docs: annotate R1 tag spellings; dashboard refresh 2026-09-07 17:57:21 -04:00
fpu-cw lane F: x87 precision sensitivity measured; STATE_CHECKSUM 3.5 closed 2026-09-08 05:07:53 -04:00
harness harness: coverage reporting + --strict-coverage in tracecmp 2026-09-08 01:28:36 -04:00
parsers parsers: engine parity (first-wins, Mars::Script tokenizer rules, trailing-pair drop); untrack pyc 2026-09-07 18:10:17 -04:00
results lane U: the unlock cascade, implemented and live-verified 2026-09-08 06:57:37 -04:00
save-reader lane S: std::string is 0x1c binary-wide; ObservedTech element fully mapped 2026-09-08 05:09:33 -04:00
state-checksum lane F: x87 precision sensitivity measured; STATE_CHECKSUM 3.5 closed 2026-09-08 05:07:53 -04:00
traces lane U: the unlock cascade, implemented and live-verified 2026-09-08 06:57:37 -04:00